How To Draw D-flip Flops Quartus

Module 5.3

D Blazon Flip-flops

Later studying this section, you should be able to:
Understand the operation of D Blazon flip-flops and can:
• Describe typical applications for D Blazon flip-flops.
• Recognize standard excursion symbols for D Type flip-flops.
• Recognize D Blazon flip-flop integrated circuits.
Recognise culling forms of D Type flip-flops.
• Border triggered D Blazon flip-flops.
• Toggle flip-flops.
• Stuff.
Construct timing diagrams to explain the functioning of D Type flip-flops.
Use software to simulate D Type flip-flops.

Fig. 5.3.one Level Triggered D Type Flip-flop

D Type Flip-flops

The major drawback of the SR flip-flop (i.e. its indeterminate output and non-allowed logic states) described in Digital Electronics Module 5.ii is overcome by the D blazon flip-flop. This flip-bomb, shown in Fig. v.three.1 together with its truth table and a typical schematic circuit symbol, may be chosen a Data flip-bomb because of its ability to 'latch' and remember data, or a Delay flip-flop because latching and remembering data can be used to create a filibuster in the progress of that data through a circuit. To avoid the ambiguity in the title therefore, information technology is usually known merely as the D Blazon. The simplest grade of D Type flip-bomb is basically a high activated SR blazon with an boosted inverter to ensure that the S and R inputs cannot both exist high or both low at the same fourth dimension. This simple modification prevents both the indeterminate and not-allowed states of the SR flip-flop. The S and R inputs are now replaced by a unmarried D input, and all D blazon flip-flops have a clock input.

Operation.

Every bit long as the clock input is low, changes at the D input make no difference to the outputs. The truth table in Fig. 5.3.1 shows this as a 'don't care' country (X). The basic D Type flip-flop shown in Fig. 5.3.1 is chosen a level triggered D Blazon flip-bomb considering whether the D input is active or not depends on the logic level of the clock input.

Provided that the CK input is high (at logic one), then whichever logic state is at D will announced at output Q and (dissimilar the SR flip-flops) Q is always the inverse of Q).

In Fig. 5.iii.1, if D = 1, and so Southward must be ane and R must be 0, therefore Q is Set up to 1.

Alternatively,

If D = 0 then R must be ane and S must be 0, causing Q to be reset to 0.

The Data Latch

The name Data Latch refers to a D Type flip-flop that is level triggered, as the information (1 or 0) actualization at D tin be held or 'latched' at whatsoever time whilst the CK input is at a high level (logic 1).

As can be seen from the timing diagram shown in Fig 5.3.2, if the data at D changes during this fourth dimension, the Q output assumes the same logic level as the D.

Fig. 5.3.2 Timing Diagram for a Level Triggered D Type Flip-flop

Ripple Through

Fig. 5.3.2 also illustrates a possible problem with the level triggered D type flip-bomb; if there are changes in the data during catamenia when the clock pulse is at its loftier level, the logic state at Q changes in sympathy with D, and only 'remembers' the last input state that occurred during the clock pulse, (menstruum RT in Fig. 5.three.two). This issue is called 'Ripple Through', and although this allows the level triggered D Type flip-flop to exist used as a data switch, only allowing information through from D to Q as long every bit CK is held at logic ane, this may not be a desirable property in many types of excursion.

Fig. v.three.3 Edge Triggered D Blazon Flip-Flop with Set and Reset

The Border Triggered D Type Flip-bomb

Fortunately ripple though can be largely prevented by using the Border Triggered D Type flip-bomb illustrated in Fig 5.three.three.

The clock pulse applied to the flip-bomb is reduced to a very narrow positive going clock pulse of merely about 45ns elapsing, by using an AND gate and applying the clock pulse straight to input 'a' only delaying its arrival at input 'b' by passing it through 3 inverters. This inverts the pulse and too delays information technology by iii propagation delays, (virtually 15ns per inverter gate for 74HC serial gates). The AND gate therefore produces logic i at its output only for the 45ns when both 'a' and 'b' are at logic one after the ascent edge of the clock pulse.

Synchronous and Asynchronous Inputs

A further refinement in Fig. 5.3.3 is the addition of two further inputs Gear up and RESET, which are actually the original Southward and R inputs of the basic low activated SR flip-flop.

Fig. five.3.four Edge Triggered D Blazon Flip-Flop

Notice that there is at present a subtle difference between the active low Prepare (Due south) and Reset (R) inputs, and the D input. The D input is SYNCHRONOUS, that is its action is synchronised with the clock, simply the S and R inputs are ASYNCHRONOUS i.e. their activity is NOT synchronised with the clock. The SET and RESET inputs in Fig five.3.4 are 'low activated', which is shown by the inversion circles at the Southward and R inputs to indicate that they are really Southward and R.

The flip-bomb is positive edge triggered, which is shown on the CK input in Fig 5.3.4 by the wedge symbol. A wedge accompanied past an inversion circle would bespeak negative (falling) edge triggering, though this is by and large not used on D Type flip-flops.

Fig. v.3.5 Typical Schematic Symbols for D Type Edge Triggered Flip-Flops

Timing Diagram

The 'Edge triggered D type flip-flop with asynchronous preset and clear capability', although developed from the basic SR flip-flop becomes a very versatile flip-flop with many uses. A timing diagram illustrating the activity of a positive edge triggered device is shown in Fig. 5.3.five.

At the positive going edges of clock pulses a and b, the D input is loftier so Q is also high.

Only before pulse c the D input goes low, and then at the positive going edge of pulse c, Q goes low.

Betwixt pulses c and d the asynchronous Due south input goes depression and immediately sets Q high.

The flip-flop then ignores pulse d while S is depression, just as S returns high, and D has also returned to its loftier state before pulse e, Q remains high during pulse e.

At the positive going border of pulse h, the low level of input D remains, keeping Q depression, merely betwixt pulses h and i, the S input goes low, overriding any action of D and immediately making Q high.

D is still high at the positive going edge of pulse f, and considering the flip-flop is positive edge triggered, the alter in the logic level of D during pulse f is ignored until the positive going border of pulse g, which resets Q to its low level.

Clock pulse i is once more ignored, due to South being in its active depression land and Q remains high, under the control of S until but before pulse j. At the positive going edge of pulse j, input D regains control, but every bit D is high and Q is already high, no change in output Q occurs.

Finally, just before pulse k, the asynchronous reset input (R) goes low and resets Q to its low level (logic 0), which over again causes the D input to be ignored.

Edge triggered D Type Flip-flop Summary:

• At the positive going edge of a CK pulse, Q will assume the same level as input D, unless either asynchronous input has control.

• A logic 0 on the asynchronous input Southward at any time will crusade Q to be set up to logic i from the time S goes low, until the beginning CK pulse after S returns to logic 1.

• A logic 0 on the asynchronous input R will cause Q to be reset to logic 0 from the fourth dimension R goes low, until the first CK pulse later R returns to logic ane.

• The action of the asynchronous inputs overrides any effect of the D input.

• Both asynchronous inputs should not exist low at the same time, equally both Q and Q will exist at logic one. This is a non-allowed state.

Fig. 5.three.vi The D Blazon Principal Slave Flip-flop

The D Blazon Primary Slave Flip-Flop

Yet a further version of the D Type flip-flop is shown in Fig. 5.3.6 where ii D type flip-flops are incorporated in a single device, this is the D type master-slave flip-bomb. Circuit symbols for the master-slave device are very similar to those for edgetriggered flip-flops, but are at present divided into two sections past a dotted line, as also illustrated in Fig 5.3.half-dozen.

FF1 (the chief flip-bomb) is a positive border triggered device, and an inverted version of the CK pulse is fed from the main CK input to FF2 (the slave), besides positive border triggered. Notice that although the clock inputs on the circuit symbols suggest that this is a negative edge triggered device, data is actually taken into FF1 on the POSITIVE going edge of the CK pulse. The data likewise of course appears at q1 at this time, but as the CK pulse is inverted at ck2, FF2 is seeing a falling edge at the same time, then ignores the information on d2.

Afterward the positive going border of the external CK pulse, FF1 ignores whatsoever further data at D, and at the negative going border of the external CK pulse, the data beingness held at q1 is taken into the d2 input of FF2 which now sees a positive going edge of the inverted CK pulse. Therefore information is taken into D at the positive going (rise) border of the CK pulse, and so appears at Q at the negative going (falling) edge of the CK pulse.

Fig. five.3.7 Timing Diagram for a D Type Master-Slave Flip-flop

Because the primary slave flip-flop as a unmarried device, the relationship between the clock (CK) input and the Q output does wait rather similar a negative edge triggered device, as any change in the output occurs at the falling edge of the clock pulse. Yet, every bit illustrated in Fig. 5.3.7 this is non actually negative edge triggering, because the data appearing at Q every bit the clock pulse returns to logic 0, is actually the data that was nowadays at input D at the RISING edge of the CK pulse. Any further changes that may occur in information at the D input during the clock pulse are ignored. D type master-slave flip-flops are as well bachelor with asynchronous S and R inputs making it a very versatile device indeed.

The Toggle Flip-flop

Fig. 5.3.viii An Edge Triggered D Type Converted to a Toggle Flip-flop

Toggle flip-flops are the bones components of digital counters, and all of the D type devices are adaptable for such use. When an electronic counter is used for counting, what are actually existence counted are pulses appearing at the CK input, which may be either regular pulses derived from an internal clock, or they tin exist irregular pulses generated by some external event.

When a toggle flip-flop is used equally 1 phase of a counter, its Q output changes to the opposite state, (it toggles) high or low on each clock pulse. Well-nigh border-triggered flip-flops can be used every bit toggle flip-flops including the D type, which can be converted to a toggle flip-flop with a simple modification. In theory all that is necessary to convert an edge triggered D Type to a T blazon is to connect the Q output direct to the D input as shown in Fig. 5.3.8. The actual input is now CK. The event of this mode of operation is also shown in the timing diagram in Fig. v.3.eight using a positive border triggered D blazon flip-flop.

Toggle Flip-flop Operation

Suppose that initially CK and Q = 0. And so Q and D must be 1. At the rising edge of a CK pulse, the logic 1 at D is allowed into the flip-flop and, at the end of the flip-flop'southward propagation delay, appears at Q, and Q changes to logic 0 at the same time.

This logic 0 is now fed back to D, simply it is important that it is not immediately accepted into the D input, otherwise oscillation could occur with D continually irresolute between 1 and 0. Yet, because of the flip-bomb's propagation delay, when the logic 0 from Q arrives at D, the very short border-triggering catamenia will have completed, and the change in data at D volition be ignored.

At the next CK rising edge of the clock point, the 0 at D at present passes to Q, making Q and D logic 1 once more. The Q output of the flip-bomb therefore toggles at each positive going edge of the CK pulse.

Because the Q output changes country at each clock pulse rising edge, the 0 flow and the i flow of the Q output volition always be of equal length, and the output volition be a foursquare wave with a 1:1 mark to space ratio, its frequency will be half that of CK.

To utilise toggle flip-flops as elementary binary counters, a number of toggle flip-flops may be connected in cascade, with the Q output of the get-go flip-flop in the series, being connected to the CK input of the next flip-flop and then on. This is also the principle of frequency sectionalization. Exactly how counters and dividers can be constructed from toggle flip-flops is explained in Sequential Logic Module five.6.

Information Timing

In exercise all the same, using direct feedback from Q to D can crusade problems as, to ensure stable operation and avert unwanted oscillation, it is of import in any digital circuit, that any changes in logic level taking identify at D must be both stable, (free from any overshoot or ringing etc.) and at a valid logic level during a short menstruation, earlier and after the clock signal causes a change. These periods are called the set upward and hold times.

Fig. five.3.9 Clocked Logic Gear up and Hold Times

Although it is easy to remember of the clock signal initiating a modify at a detail time, east.g. when its ascension edge occurs, data is actually clocked into input D when the CK waveform reaches a sure voltage level. In 74HC series gates this level is 50% of V_DD, every bit illustrated in Fig five.3.ix. This shows in expanded time detail, the transitions taking place at the D and CK inputs of a D blazon positive edge triggered flip-flop.

To guarantee correct triggering, it is important that the information at the D input has settled at a valid logic level before the clock point triggers whatever change. Therefore there must be some time allowed from when the D input first becomes valid to allow time for any slow rising pulse, whatever overshoot or ringing to occur before the clock pulse samples the logic level.

For case, the fourth dimension between point (a) in Fig.5.3.9, where D initially falls below 50% of V_DD and the time when CK rises to its trigger threshold of fifty% 5_DD (point b) is chosen the set up time (t_setup or t_su), and in 74HC series ICs this will typically be between 5ns and 15ns.

After the trigger point at that place must be a farther period (b to c in Fig. 5.3.9) where the data at D must remain at the same valid logic level to ensure that the correct logic level has been accustomed. This is called the hold time (t_hold or t_h) and is typically around 3ns in 74HC serial ICs.

In sequential logic circuits, precise timing is vitally of import. The design of a circuit must take into consideration not just prepare and hold times simply also the propagation times of gates or flip-flops in each path that a digital signal takes through a circuit. Failure to get the timing right tin can lead to problems such as 'glitches' i.e. sudden sharp spikes, as a device such as a flip-flop momentarily produces a change from one logic level to some other and back once more. Such glitches may be very short (a few nanoseconds) but sufficient to trigger another device to a wrong logic level.

With devices such as flip-flops using both triggering and feedback, incorrect timing can as well lead to instability and unwanted oscillations. Avoiding such problems is a major reason for the use of border triggering and master slave devices.

D Type Flip-flop ICs

A option of D type Flip-flop ICs are listed below.

74HC74 Dual D Type Flip-flop with Ready and Reset from ON Semiconductors.
74LS75 Quad D Type Information Latches from Texas Instruments.
74HC174 Hex D Type Flip-bomb with Reset from NXP.
74HC175 Quad D Type Flip-bomb with Reset from NXP.
74HC273 Octal D Blazon Flip-flop with Reset from Texas Instruments.
74HC373 Octal Transparent D Type Information Latches with 3-State Outputs from Texas Instruments.
74HC374A Octal 3-Land Not-Inverting D Blazon Flip-flop from ON Semiconductors.

Source: https://www.learnabout-electronics.org/Digital/dig53.php

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